1. Field of the Invention
The present invention relates to the manufacture and handling of material sheets and/or structures, such as semiconductor wafers and tiles, for use in making intermediate structures.
2. Technical Background
Semiconductor on insulator devices are becoming more desirable as market demands continue to increase. SOI technology is becoming increasingly important for high performance thin film transistors (TFTs), solar cells, and displays, such as, active matrix displays, organic light-emitting diode (OLED) displays, liquid crystal displays (LCDs), integrated circuits, photovoltaic devices, etc. SOI structures may include a thin layer of semiconductor material, such as silicon, on an insulating material.
Various ways of obtaining SOI structures include epitaxial growth of silicon (Si) on lattice matched substrates, and bonding a single crystal silicon water to another silicon wafer. Further methods include ion-implantation techniques in which either hydrogen or oxygen ions are implanted either to form a buried oxide layer in the silicon wafer topped by Si in the case of oxygen ion implantation or to separate (exfoliate) a thin Si layer to bond to another Si wafer with an oxide layer as in the case of hydrogen ion implantation.
U.S. Pat. No. 7,176,528 discloses a process that produces an SOG (semiconductor on glass) structure. The steps include: (i) exposing a silicon wafer surface to hydrogen ion implantation to create a bonding surface; (ii) bringing the bonding surface of the wafer into contact with a glass substrate; (iii) applying pressure, temperature and voltage to the wafer and the glass substrate to facilitate bonding therebetween; and (iv) separating the glass substrate and a thin layer of silicon from the silicon wafer.
The above manufacturing process, as well as many other processes for fabricating, for example SOI structures, may require the availability of high quality semiconductor material sheets (or wafers), such as single crystal silicon wafers. The semiconductor wafers are usually round and, in some applications, must be processed to achieve rectangular wafers or “tiles.” Semiconductor tiles are often required to have strict dimensional tolerances, good crystalline orientation alignment and high form accuracy such as straightness, parallelism and perpendicularity. The semiconductor tiles may also need to be rounded on all four corners and chamfered to a specified profile along the four edges of each side in order to survive ion implantation/exfoliation re-use cycles. In addition, the semiconductor tiles must be free of contamination, foreign particles, heat-damage, chipping, micro-cracks, and any other subsurface damage or characteristics that would limit fracture strength.
The traditional processes for preparation of the semiconductor tiles employ diamond cutting/trimming a round wafer into a rectangular tile, then edge grinding, and polishing of tile edges. These processes are considered to be relatively costly because of the number of separate process steps involved, including significant cleaning steps to ensure contamination is minimized.
Accordingly, there is a need in the art for new methods and apparatus for handling and processing sheet material (such as SOI structures).